The disclosed embodiments relate to semiconductor devices and methods of forming the same.
Semiconductor devices are widely used in an electronic industry because of their small size, multi-function, and/or low manufacture costs. The semiconductor devices have been highly integrated with the development of the electronic industry. Widths and spaces of patterns of the semiconductor devices are being reduced for the high integration of the semiconductor devices. However, new exposure techniques and/or very expensive exposure techniques are required for fineness of the patterns such that it is difficult to highly integrate the semiconductor devices. Thus, various research has been conducted for new integration techniques. Air spacers may be used in certain semiconductor devices to serve as an insulation pattern. When finely patterned air spacers are used, the air spacers may be inadvertently filled with conductive material during the manufacturing process, which may lead to short circuits and failed devices.
In one embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a plurality of bit line structures formed on the substrate, each bit line structure extending in a first direction, a plurality of word lines, each word line extending in a second direction different from the first direction; and a plurality of contact structures, each provided between two adjacent bit line structures of the plurality of bit line structures. Each bit line structure includes a first semiconductor layer, a conductive layer on the first semiconductor layer, and a capping layer on the conductive layer, wherein the conductive layer is disposed above the first semiconductor layer and below the capping layer. Each contact structure includes a lower contact portion and an upper contact portion, wherein a bottom surface of the upper contact portion contacts a top surface of the lower contact portion at a contact structure interface. The semiconductor device further includes a plurality of spacer structures, each spacer structure located between a bit line structure and a contact structure and including at least an air gap, an insulating spacer between the air gap and the contact structure, and a capping spacer. Each capping spacer covers a top of a corresponding air gap, extends between a bit line structure and a contact structure from above the top of the corresponding air gap to a first height below the top of the corresponding air gap, and fills an area between the insulating spacer and the contact structure, wherein the first height is lower than a top of the conductive layer of a bit line structure adjacent to the capping spacer.
In one embodiment, the contact structure interface for each contact structure is located at a second height lower than the first height.
In certain embodiments, a first dopant region is disposed below a first bit line structure of the plurality of bit line structures; and a second dopant region is disposed below a first contact structure of the plurality of contact structures. The first dopant region may contact a first semiconductor layer of the first bit line structure; and the second dopant region may contact the first contact structure.
In one embodiment, for each capping spacer, the capping spacer fills an area between a corresponding insulating spacer and a corresponding bit line structure to a height above the first height and below a top of the corresponding insulating spacer.